1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a metal-oxide semiconductor device (MOS) device.
2. Description of Related Art
A MOS device is the most elementary device in a integrated circuit (IC) device. A MOS transistor usually includes a gate structure, a source region, and a drain region. The gate structure further includes a gate oxide layer and a metal layer sequentially formed on a semiconductor substrate, such as a silicon substrate. The source region and the drain region are formed in the semiconductor substrate respectively at each side of the gate structure. Since the source region and the drain region is interchangeable, the source region drain region are usually called together as an interchangeable source/drain region.
Conventionally, before forming the gate structure of the MOS transistor, a global ion implantation process is necessarily performed over the semiconductor substrate so as to adjust a threshold voltage of the gate structure and form a capability of anti-punch-through. The gate structure, the source region and the drain region are then formed to accomplish the MOS transistor. The conductive layer of the gate structure usually includes a doped polysilicon layer and a metal silicide layer, which is also called a silicide layer. The polysilicon layer provides a better adhesion capability with the gate oxide layer, and the suicide layer provides a better conductivity. Combining these two layers, the metal layer of the gate structure is called a polycide layer.
In above, even through the global ion implantation process has its advantages, it also causes an extra junction capacitance of the source/drain region, resulting a larger AC resistance, which decreases a data transmission speed. Moreover, as the device integration continuously increases, the device dimension has reached to a deep sub-micron level. The conventional polycide layer of the gate structure therefore has larger resistance due to a reduced dimension. This also causes to decrease the data transmission speed. Furthermore, for a dual gate structure, which includes two gate structures abutting each other, the dopants of the doped polycide layers of each gate structure may inter-diffuse each other through the silicide layers of the dual gate structure, resulting in a drifting of the threshold voltage. Moreover, the silicide layers may be agglomerated as an annealing process is performed in a high temperature environment. The agglomeration phenomenon causes an instability of electrical properties of the gate structure. A conventional solution, called a selective local implantation process, to solve the above problems is proposed to take place of the global ion implantation process. A metal gate layer also takes place of the conventional silicide layer of the polycide gate structure. The conventional proposal is described in FIGS. 1A-1D, which are cross-sectional views of a MOS transistor, schematically illustrating a conventional fabrication process of the MOS transistor.
In FIG. 1A, a semiconductor substrate 100 including a trench isolation structure 102 is provided. A photoresist layer 104 is formed on the substrate 100 and is patterned to expose a portion of the substrate 100, where a gate structure is to be formed. Using the photoresist layer 104 as a mask, ion implantation processes are performed to form a threshold-voltage doped region 116a and an anti-punch-through region 116b in the substrate 100 below the threshold-voltage doped region 116a.
In FIG. 1B, after removing the photoresist layer 104, a gate oxide layer 106, a polysilicon layer 108, and a metal layer 110 are sequentially formed over the substrate 100.
In FIG. 1C, the gate oxide layer 106, the polysilicon layer 108, and the metal layer 110 are patterned to respectively form a gate oxide layer 106a, a polysilicon layer 108a, and a metal layer 110a, all of which form a gate structure 109, which is above the threshold-voltage doped region 116a.
In FIG. 1D, a light ion implantation is performed to pre-form an interchangeable source/drain region between the gate structure 109 and the trench isolation structure 102. A sidewall spacer 112 is formed on each sidewall of the gate structure 109. Using the sidewall spacer 112 and the gate structure 109 as a mask, a heavy ion implantation is performed to accomplish an interchangeable source/drain region 114 in the substrate 100 at each side of the gate structure 109. A MOS transistor with the selective local implantation process is therefore formed. The interchangeable source/drain region 114 has lightly doped drain (LDD) structure. The metal layer 110a in the gate structure 109 can solve those conventional issues of high gate resistance, polycide thermal instability, and inter-diffusion. The MOS transistor with the selective local implantation process can reduce the junction capacitance in order to increase operation of data transmission speed.
However, the metal layer 110 cannot be easily etched, and the etched metal particles from the metal layer 110 remaining a etching tank may cause an acid-tank contamination. A contaminated etching tank may affect subsequent etching performance. Moreover, the selective local implantation process needs an extra mask, which also needs a critical alignment accuracy. A low yield rate may occurs.